The invention relates to a system for transient-current testing of an electronic circuit. Generally, transient-current measurements or so-called IDDT (IddT) measurements have found application for effecting structural testing on digital integrated circuits that feature relatively larger leakage currents at decreasing circuit detail size. IDDT testing has been proposed as an alternative or supplement to quiescent-current, or IDDQ, testing, because some circuits may not be IDDQ testable with continuous measurements through their having pull-ups or other aspects. Also, spread in leakage may increase. As would be obvious, such testing should in general find the best possible compromise between spotting all sub-standard circuits and rejecting zero correct operating circuits as based on one or more parameters that have some non-ideal mapping from functionality. Moreover, it should be preferable when only a single test principle were necessary. A relevant IDDT-methodology has been published in M. Sachdev, P. Janssen and V. Zieren, xe2x80x9cDefect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS IC""sxe2x80x9d Proc. Int. Test Conf. 1998, pp. 204-213. Now, although the above teaching is fully adequate from a theoretical point of view, practicing thereof has run into various difficulties as relating to flexibility, test apparatus cost and in particular, integratability, in that it requires for mixed signal -analog plus digital-facilities. Such difficulties stem from one or more of the following causes:
the reference uses a current probe that is less than optimum from a flexibility point of view;
the reference compares in software with a so-called xe2x80x9cgolden devicexe2x80x9d of known and adequate functionality; such approach often requires an inappropriate amount of time because many digital testers have little or no local computing facilities.
Now, according to the present invention, the simulating of a current probe by a high-pass filter has allowed appreciable freedom in choosing the 3-dB filter point, which in turn has facilitated integrating into an integrated test circuit. The new approach also allows to implement a calibration feature, which in turn enables to use only a digital tester enhanced with ADC and DAC but without needing extensive data processing facilities. Furthermore, by calibrating the actual potential value of the high-pass filter, in each IDDT cycle a correct DUT will on the associated IDDT sample instant produce a substantially uniform voltage value. This in turn allows executing xe2x80x9creal time comparisonxe2x80x9d by the digital tester. In practice, such usage saves much time, because no inappropriate computing load needs anymore to be impressed on the all-digital tester. Note that the tester does no longer need to be a mixed-signal tester that would have to accommodate handling both digital and analog signals. In fact, the circuit under test is usually digital, and the earlier measurement practice would also need processing of analog voltages.
In consequence, amongst other things, it is an object of the present invention to allow an integratable, straightforward, low-cost and reliable solution for application of the IDDT methodology to ever more compact digital CMOS circuitry.
Now therefore, according to one of its aspects the invention is characterized by having a current measuring circuit of the transient-current tester implemented in integrated circuit technology as a high-pass filter. The invention may be useful for analog circuits or circuit parts, or for other technology than CMOS or even MOS.
The invention also relates to an integrated circuit item for effecting the above interfacing between the digital tester and the circuit proper under test.